The Hardware Design of Parameter-Adjustable FIR Filter System
نویسنده
چکیده
This design using FPGA parallel architecture, high computing speed and high-speed reliability of USB2.0 interface, designed an FPGA + USB2.0 + computer FIR digital filter system, organically combining the speed of FPGA and flexibility of Computer through USB2.0 bus. The results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, that it can effectively filter out the noise signals.
منابع مشابه
Interference Mitigation of Replay Attacks in GPS Receiver using of Finite Impulse Response Filter
The vulnerability of civil GPS receiver to interference may be intentional or unintentional. Among all types of interference, replay attack intended as the most dangerous intentional one. The signal structure of replay attack is almost the same with the satellite signal. The interference effects can be reduce with the design of an appropriate filter in the receiver. This paper presents two meth...
متن کاملAdjustable PSO Based FIR Filter Design Using Advanced Error Function Approach of Minimizing Frequency Response Ripples
Digital Filter is an important part of digital signal processing (DSP) system and it usually comes in two categories: finite impulse response (FIR) and infinite impulse response (IIR). FIR filter is an attractive choice because of the ease in design and stability. By designing the filter taps to be symmetrical about the centre tap position, a FIR filter can be guaranteed to have linear phase. L...
متن کاملAdjustable Fractional Delay FIR Filters Design Using Multirate and Frequency Optimization Techniques
Abstract— One of the most efficient implementation for adjustable fractional delay FIR filter is the Farrow structure, allowing on line fractional delay value update with a fixed branch filters set. A wideband fractional delay FIR filter requires high number of branch filters and high branch filters length, which results in a complex arithmetic implementation. This paper describes a multirate...
متن کاملOptimal fast digital error correction method of pipelined analog to digital converter with DLMS algorithm
In this paper, convergence rate of digital error correction algorithm in correction of capacitor mismatch error and finite and nonlinear gain of Op-Amp has increased significantly by the use of DLMS, an evolutionary search algorithm. To this end, a 16-bit pipelined analog to digital converter was modeled. The obtained digital model is a FIR filter with 16 adjustable weights. To adjust weights o...
متن کاملComparison Between FPGA Logic Resources And Embedded Resources Used By Discrete Arithmetic (DA) Architecture To Design FIR Filter
FIR Filter is a fundamental function in many applications, mainly in the field of Digital Signal Processing (DSP). The main problem of this function is its computational complexity, needed to process a signal. Currently, FPGAs are widely used for a variety of computationally complex applications. New generation of FPGAs contain not only basic configurable logic resources but also complex embedd...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- JCP
دوره 8 شماره
صفحات -
تاریخ انتشار 2013